77 lines
1.6 KiB
Nix
77 lines
1.6 KiB
Nix
{ lib
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, stdenv
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, fetchFromGitHub
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, cmake
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, python3
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, pkg-config
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, libuuid
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, openjdk
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, gperftools
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, flatbuffers
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, fetchpatch
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}:
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stdenv.mkDerivation rec {
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pname = "surelog";
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version = "1.45";
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src = fetchFromGitHub {
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owner = "chipsalliance";
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repo = pname;
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rev = "v${version}";
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hash = "sha256-/SSKcEIhmWDOKN4v3djWTwZ5/nQvR8ibflzSVFDt/rM=";
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fetchSubmodules = true;
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};
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# This prevents race conditions in unit tests that surface since we run
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# ctest in parallel.
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# This patch can be removed with the next version of surelog
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patches = [
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(fetchpatch {
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url = "https://github.com/chipsalliance/Surelog/commit/9a54efbd156becf65311a4272104810f36041fa6.patch";
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sha256 = "sha256-rU1Z/0wlVTgnPLqTN/87n+gI1iJ+6k/+sunVVd0ulhQ=";
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name = "parallel-test-running.patch";
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})
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];
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nativeBuildInputs = [
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cmake
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pkg-config
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openjdk
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(python3.withPackages (p: with p; [
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psutil
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orderedmultidict
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]))
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];
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buildInputs = [
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libuuid
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gperftools
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flatbuffers
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];
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cmakeFlags = [
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"-DSURELOG_USE_HOST_FLATBUFFERS=On"
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];
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doCheck = true;
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checkPhase = ''
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runHook preCheck
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make -j $NIX_BUILD_CORES UnitTests
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ctest --output-on-failure
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runHook postCheck
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'';
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postInstall = ''
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mv $out/lib/surelog/* $out/lib/
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mv $out/lib/pkg $out/lib/surelog/
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'';
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meta = {
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description = "SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler";
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homepage = "https://github.com/chipsalliance/Surelog";
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license = lib.licenses.asl20;
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maintainers = with lib.maintainers; [ matthuszagh ];
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platforms = lib.platforms.linux;
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};
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}
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