55 lines
1.5 KiB
Nix
55 lines
1.5 KiB
Nix
{ lib, stdenv, fetchFromGitHub, python3, boost, cmake }:
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let
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rev = "03e0070f263fbe31c247de61d259544722786210";
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# git describe --tags
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realVersion = "1.0-532-g${builtins.substring 0 7 rev}";
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in stdenv.mkDerivation rec {
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pname = "trellis";
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version = "2021-09-01";
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srcs = [
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(fetchFromGitHub {
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owner = "YosysHQ";
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repo = "prjtrellis";
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inherit rev;
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sha256 = "joQMsjVj8d3M3IaqOkfVQ1I5qPDM8HHJiye+Ak8f3dg=";
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name = "trellis";
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})
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(fetchFromGitHub {
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owner = "YosysHQ";
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repo = "prjtrellis-db";
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rev = "fdf4bf275a7402654bc643db537173e2fbc86103";
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sha256 = "eDq2wU2pnfK9bOkEVZ07NQPv02Dc6iB+p5GTtVBiyQA=";
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name = "trellis-database";
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})
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];
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sourceRoot = "trellis";
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buildInputs = [ boost ];
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nativeBuildInputs = [ cmake python3 ];
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cmakeFlags = [
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"-DCURRENT_GIT_VERSION=${realVersion}"
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];
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preConfigure = ''
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rmdir database && ln -sfv ${builtins.elemAt srcs 1} ./database
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cd libtrellis
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'';
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meta = with lib; {
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description = "Documentation and bitstream tools for Lattice ECP5 FPGAs";
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longDescription = ''
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Project Trellis documents the Lattice ECP5 architecture
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to enable development of open-source tools. Its goal is
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to provide sufficient information to develop a free and
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open Verilog to bitstream toolchain for these devices.
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'';
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homepage = "https://github.com/YosysHQ/prjtrellis";
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license = licenses.isc;
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maintainers = with maintainers; [ q3k thoughtpolice emily ];
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platforms = platforms.all;
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};
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}
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